The use of current mode switching regulators to control a DC output voltage at a level higher than, lower than, or the same as an input voltage is well known. Typically, one or more switches are activated to supply current pulses via an inductor to charge an output capacitor. The output voltage level is maintained at a desired level by adjusting the on and off times of the switching pulses in accordance with output voltage and load conditions.
FIG. 1 is a block diagram of a typical current mode switching regulator. Switching control circuit 10 may comprise any of various known controllers that provide pulse width modulated output pulses to regulate a DC output voltage VOUT at a level that may be greater than, lower than, or the same as a nominal input voltage VIN. Typically, the control circuit includes a latch, having set and reset inputs, coupled to a controlled switch that supplies switched current ISW to inductor 12. Capacitor 14 is connected between the output VOUT and ground. Resistors 16 and 18 are connected in series between VOUT and ground. A load 20 is supplied from the regulator output.
The set input is coupled to clock 22, which may generate pulses in response to an oscillator, not shown. During normal operation, the latch is activated to initiate a switched current pulse when the set input receives each clock pulse. The switched current pulse is terminated when the reset input receives an input signal, thereby determining the width of the switched current pulse. The reset input is coupled to the output of comparator 24. An output voltage feedback signal VFB is taken at the junction of resistors 16 and 18 and coupled to negative input of error amplifier 26. A voltage reference VREF is applied to the positive input of error amplifier 26. Capacitor 28 is coupled between the output of error amplifier 26 and ground.
The level of charge of capacitor 28, and thus its voltage VC, is varied in dependence upon the output of amplifier 26. As load current increases, the output voltage, and thus VFB, decreases. As the feedback voltage VFB decreases, VC increases. Thus, VC is proportional to load current. VC is coupled to the inverting input of comparator 24. The non-inverting input is coupled to adder 30. Adder 30 combines signal ISW, which is proportional to the sensed switch current, with a compensation signal. Upon switch activation in response to a clock set signal, switch current builds through inductor 12. When the level of the signal received from adder 30 exceeds VC, comparator 24 generates a reset signal to terminate the switched current pulse. During heavier loads VC increases and the switched current pulse accordingly increases in length to appropriately regulate the output voltage VOUT. As VC is an indication of load, it can be monitored by internal circuitry, not shown, to detect light load conditions. In response to VC reaching a predetermined light load condition threshold, the operation can be changed to a “sleep mode,” in which some circuit elements can be deactivated to consume power.
For normal regulator operation at duty cycles of fifty percent or higher, compensation is needed in the switching control to avoid sub-harmonic oscillation. A typical approach is termed “slope compensation,” wherein a signal of increasing magnitude is added to the current signal ISW, or subtracted from the signal VC, during each switching cycle. FIG. 2 is a circuit diagram of a prior art slope compensation generator that may be input to adder 30 to modify the current signal applied to the non-inverting input of comparator 24. The output of the circuit is a current signal Sx corresponding to the current in the series circuit path of transistor 32, resistor 34 (R) and voltage bias (VB) source 36. The base of transistor 32 is coupled to the output of unity gain buffer amplifier 38. The positive input of amplifier 38 is coupled to receive a ramp signal Vramp. The negative input of amplifier 38 is coupled to the junction between transistor 32 and resistor 34.
FIG. 3 is a simplified waveform diagram illustrative of the compensation function of the circuit of FIG. 2. The Vramp signal is a sawtooth format signal that is generated at the beginning of each clock cycle and extends at linear slope to the end of the cycle, corresponding to one hundred percent duty cycle. As an example, the Vramp magnitude may vary between zero and one volt. Transistor 32 begins conduction at a point Ts in the cycle at which Vramp overtakes the fixed voltage VB. As compensation is needed at fifty percent duty cycle operation or greater, VB typically is arbitrarily chosen at one half the value of the maximum Vramp level, or one half-volt in the present example. As Vramp continues to increase after time Ts, the base signal applied to transistor 32 increases and, thus, the output current Sx increases linearly to a maximum Smax at the end of the switching cycle. Sx is determined by (Vramp−VB)/R. The compensation curve Sx starting point Ts is thus determined by VB, and its slope is determined by R. In this example Ts occurs at fifty percent of the switching cycle, regardless of the actual duty cycle.
Because this slope compensation curve starts at fifty percent of the switching cycle, the Sx builds up to a high level at a maximum duty cycle of one hundred percent. The high level of the compensation signal is disadvantageous at or near maximum duty cycle operation. The voltage VC, the output of feedback amplifier 26 applied to the negative input of comparator 24, has the same value as the sum of the switch current ISW and the slope compensation signal Isx at the positive input of comparator 24 when the switched pulse terminates. As a high offset has been introduced, VC will not accurately indicate true output load current. At the high duty cycle operation, the switching current limit level is reduced. At higher duty cycle operation, the sleep mode threshold, based on VC, will be inaccurate. The need thus exists for an improved compensation scheme that overcomes the drawbacks of the prior art slope compensation.
Disclosure
The above-described needs of the prior art are fulfilled, at least in part, by detecting switching duty cycle of a switching regulator, developing a compensation signal having a time duration that is related to the detected switching duty cycle, and generating a duty cycle control signal for the regulator that is dependent in part on the developed compensation signal. The compensation signal has a slope profile and is initiated during each switching cycle at a set point in the cycle that is related to the switching duty cycle.
The duty cycle may be detected by generating a repetitive pulse signal coordinated with the regulator switching, and integrating the pulse signal. The point in each cycle at which the compensation signal is initiated may be set by generating a ramp signal at the onset of each switching cycle, modifying the duty cycle signal, and comparing the repetitive ramp signal with the modified duty cycle signal. When the ramp signal is equal in magnitude to the modified duty cycle signal, the compensation signal commences. Preferably, the duty cycle signal is modified by offsetting the duty cycle signal by a fixed voltage.
In an exemplified implementation, a variable compensation circuit is coupled to an input of a switching controller input for terminating a switching pulse during each switching cycle. In a preferred configuration, an amplifier circuit output is coupled to the controller input. A ramp generator provides a ramp signal to an input of the amplifier circuit, and a variable offset circuit provides a variable offset signal to the amplifier input of the amplifier. The variable offset circuit is coupled in series with the amplifier circuit output. The amplifier output signal is proportional to the difference between the ramp signal and the variable offset signal. The compensation circuit thus outputs a signal that has an offset level that varies as a function of the duty cycle of the regulator switching operation.
The amplifier circuit may be configured with an amplifier having a positive input terminal coupled to the ramp generator, a negative input terminal coupled to the variable offset circuit, and an output. A control terminal of a transistor is coupled to the amplifier output. The transistor is coupled between the variable offset circuit and the amplifier circuit output. An impedance is coupled in series with the transistor, thereby determining the slope of the compensation circuit output signal.
The variable offset circuit may be exemplified by a duty cycle detection circuit and a constant offset voltage circuit, each coupled to an adder output circuit is coupled to the amplifier input. The duty cycle detection circuit may include an integrator circuit configured to receive a repetitive pulse signal that is coordinated with the regulator switching.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.